(1) Field of the Invention
The present invention generally relates to a pulse stuffing synchronization control system, and more particularly to a pulse stuffing synchronization control system in which a plurality of items of lower digital hierarchy data are multiplexed in accordance with a time-division multiplexing (TDM) method and multiplexed data is output in synchronization with a transmission clock for higher digital hierarchy data.
(2) Description of Related Art
There is a system in which a plurality of items of lower digital hierarchy data are multiplexed in accordance with the TDM method and multiplexed data is transmitted. In this system, when the product of the transmission rate for the lower digital hierarchy data and the multiplexing number thereof does not correspond to the transmission rate for the higher digital hierarchy, a pulse stuffing synchronization control is performed so that the multiplexed data is output in synchronization with the transmission clock for the higher digital hierarchy data.
A system as shown in FIG. 1 has been proposed, in which system video information output from a video tape recorder (VTR) set 101 is transmitted from a transmitter 102 to a receiver 103 via a line. The video information received by the receiver 103 is displayed on a cathode ray tube (CRT) display unit 104. In this system, the VTR set 101 outputs three components of an analog video signal, such as an R component, a G component and a B component. In the transmitter 102 to which the three components R, G and B are supplied from the VTR set 101, the three components R, G and B are digitized in synchronization with a sampling clock. The three digital video signal components are then multiplexed in accordance with the TDM method and the multiplexed data is transmitted in synchronization with a transmission clock. The sampling clock used for digitizing the three components R, G and B is generally in a synchronization with the transmission clock. Thus, the pulse stuffing synchronization control is needed to transmit the multiplexed data of the three digital video signal components R, G and B in synchronization with the transmission clock.
A conventional system in which the pulse stuffing synchronization control is performed is shown in FIG. 2. This conventional system is provided in the transmitter 102 shown in FIG. 1. In the system shown in FIG. 2, the three digital video signal components R, G and B (corresponding to the lower digital hierarchy data) are multiplexed with the TDM method except for each horizontal blanking period, and the multiplexed data is output in synchronization with the transmission clock using the pulse stuffing synchronization control.
Referring to FIG. 2, the system comprises a memory circuit 70, an elastic memory circuit 71, a clock generator 72, a phase comparator 73, a clock controller 74 and a dividing circuit 75. The digital video signal components R, G and B are supplied to the memory circuit 70 in parallel. The memory circuit 70 is used for multiplexing the digital components R, G and B in accordance with the TDM method. The clock generator 72 is provided with PLL (phase-locked loop) circuits, and generates a first clock signal CLK1 and a second clock signal CLK2 based on a horizontal synchronizing signal H of the video signal supplied from the VTR set 1. The frequencies of the first and second clock signals CLK1 and CLK2 differ from each other. The first clock signal CLK1 is supplied to a writing clock terminal (W) of the memory circuit 70 so that the digital video signal components R, G and B are written into the memory circuit 70 in synchronization with the first clock signal CLK1. The clock rate of the second clock signal CLK2 corresponds to an average digital transmission rate obtained by multiplexing the digital video signal components R, G and B. The ratio of the frequency of the first clock signal CLK1 to the frequency of the second clock signal CLK2 is not always an integer. Thus, the transmitter 2 is provided with two PLL circuits for respectively generating the first and second clock signals CLK1 and CLK2. The second clock signal CLK2 is supplied to both a read clock terminal (R) of the memory circuit 70 and a write clock terminal (W) of the elastic memory circuit 71. That is, the digital video signal components R, G and B are read out in synchronization with the second clock signal CLK2 from the memory circuit 70 so as to be multiplexed. The multiplexed data read out from the memory circuit 70 is written in synchronization with the second clock signal CLK2 into the elastic memory circuit 71. The elastic memory circuit 71 is used for the pulse stuffing synchronization control. A third clock signal CLK3 for higher digital hierarchy data is processed by the clock controller 74 and a clock signal CLK3' output from the clock controller 74 is supplied to a read clock terminal (R) of the elastic memory circuit 71. That is, the multiplexed data D1 is read out in synchronization with the clock signal CLK3' from the elastic memory circuit 71.
The divider 75 divides the second clock signal CLK2 by N. The phase comparator 73 compares the phase of a divided transmission clock signal LF, obtained by dividing a transmission clock signal, with the phase of the 1/N clock signal output from the divider 75. The phase comparator 73 activates a stuffing request signal STF in accordance with the difference between the phases of the divided transmission clock signal LF and the 1/N clock signal. The stuffing request signal STF is supplied from the phase comparator 73 to the clock controller 74. When the stuffing request signal STF is activated the clock controller 74 suppresses pulses of the third clock signal CLK3 and outputs the clock signal CLK3'. The clock signal CLK3' is supplied to the read clock terminal (R) of the elastic memory circuit 71. The higher digital hierarchy data D1 read out in synchronization with the clock signal CLK3' from the elastic memory 71 is supplied to a transmission frame multiplexer (not shown) along with the stuffing request signal STF. The higher digital hierarchy data D1 and the stuffing request signal STF are multiplexed by the transmission frame multiplexer and output to the line. The multiplexed data is transmitted to the receiver 3 in synchronization with the transmission clock signal.
In the above system, the digital video signal components R, G and B corresponding to the lower digital hierarchy data are multiplexed in accordance with the TDM method by use of the memory circuit 70 and the pulse stuffing synchronization control of the multiplexed signal output from the memory circuit 70 is performed by use of the elastic memory circuit 71. That is, the conventional system requires two memory circuits (the memory circuit 70 and the elastic memory circuit 71) capable of being operated at a high speed. Thus, the size of the circuit constituting the system and the production cost of the system are large.